Eran Belaish, Director of Product Marketing, TestInsight,TestInsight
Introduction – The Bumpy Road From the Lab to the Fab
Design engineers are a world apart from test engineers, and the consequences of this open loop are especially evident when production tests fail and debug cannot tell why. Such failures often lead to blamestorming, wasting valuable resources as the different teams blame each other while the root cause of the failures is hard to trace.
Designers work with EDA environments while test engineers have their own tools and methodologies. This gap often leads to a bumpy road from the lab to the fab and can result in customer returns, longer time-to-market, higher costs, and lower yield.
Why Test Program Validation by EDA Is Not Enough
EDA tools provide convenient abstractions for designers and might overlook some production-related considerations. They often ignore design-to-test conversion and the hardware limitations of Automated Test Equipment (ATE) used in production.
As a result, when tests pass on EDA but fail on ATE it could be quite challenging to pinpoint the cause. Is it a faulty design test? A pattern conversion issue? Or perhaps a manufacturing problem? Investigating these might even require different expertise.
The many unknowns that arise when tests fail in the production environment make it clear that test program validation by EDA alone is not enough. This partial validation contributes to the open loop between EDA and ATE and perpetuates many common test program issues.
Blamestorming-free Early Pattern Validatio
Wish lists of both designers and test engineers are likely to include early pattern validation prior to production. This is because post-silicon debugging on actual ATE can be much more time consuming and directly affect time to market, which could easily lead to a counterproductive blamestorming. Why wait for silicon to find out? This question probably rings a bell to many engineers who have been surprised by production testing failures when pre-silicon results were spotless.
How is it possible then to make blamestorming a thing of the past and avoid all the downsides of relying on post-silicon pattern validation? This is where a virtual ATE can be very handy as it can accurately predict production test results long before first silicon is available.
Introducing TestInsight's Virtual Tester (VT)
VT, TestInsight's virtual ATE, enables early test program validation. It creates an ATE-aware test bench allowing pre-silicon testing with the same results as post-silicon ATE. This makes production test debug much shorter and more predictable as the test program has already been validated using VT to be ATE-compatible prior to production.
As demonstrated in the diagram above, VT converts test program files into an ATE-aware Verilog model that emulates how the ATE drives the DUT, thus closing the open loop between design and test. VT identifies pattern conversion issues and ensures that the tests are compatible with the specific ATE used in production, which allows focusing only on the model upon ATE failures.
In this process, the ATE-aware Verilog test bench created by VT is simulated with the DUT model. The test bench drives the device model inputs and compares the device output states to the expected data in the tester pattern. VT then produces a pass/fail indication per signal per test vector just like when executing a pattern on the actual tester. It also produces a simulation trace of all DUT signals and tester cycles.
A virtual ATE, such as TestInsight's VT, can remedy that as it creates an ATE-aware test bench that allows early test program validation and closes the loop between design and test
How to Set up VT and EDA Environment
A typical setup of the VT and EDA environments includes a few simple stages. First, VT is configured and executed to produce a new ATE-aware test bench based on the existing test program. Then in the EDA environment, the driver and monitor are disconnected from the DUT model and replaced with the new ATE-aware model. Finally, the new ATE-aware test bench is compiled and simulated with the DUT model.
As long as the EDA environment is not ATE-aware there is a risk for mismatches between pre-silicon testing results and post-silicon ones. A virtual ATE, such as TestInsight's VT, can remedy that as it creates an ATE-aware test bench that allows early test program validation and closes the loop between design and test.